The present invention relates to the field of computer systems, and, more particularly, to a computer device including parallel busses.
The peripheral component interconnect (PCI) bus is a high performance 32 or 64 bit bus with multiplexed address and data lines. Revision 2.2 of the PCI Local Bus Specification, which is incorporated herein by reference, defines the PCI interface protocol, electrical, mechanical, and configuration specifications for PCI bus components. The PCI bus is processor independent, which allows for an efficient transition to future processor generations, and may be used with multiple processor architectures. This processor independence allows the PCI bus to be optimized for input/output (I/O) functions, enabling concurrent operations of the PCI bus with the processor and memory devices, and accommodates multiple high speed peripheral device cards. These high speed peripheral device cards may also include a processor. The term peripheral device card used hereafter thus refers to device cards and processor device cards.
An electronic system, such as a computer device, typically includes several device cards which communicate with one or more processors. As shown in FIGS. 1 and 2, a plurality of device card connectors 14a-14h are on the printed circuit board or printed circuit motherboard 12 for receiving device cards or processor device cards, such as device card 16. Alternatively, a backpanel or interface board of the computer device may carry the plurality of device card connectors 14a-14h. 
Two PCI busses 18a, 18b are arranged in parallel across the motherboard 12, i.e., each device card connector 14a-14h is connected to two separate PCI busses. Dual busses provide increased performance and increased fault tolerance. Device card 16, for example, is connected to device card connector 14a and communicates with a processor or other devices via one of two PCI busses 18a or 18b through respective bus connections 19a or 19b. Based upon the capacitive loading, connector physics, allowed timing budget, and bus timing definitions, there are a limited number of available device card connectors 14a-14h. Conformance to the maximum loading requirements typically results in a maximum number of eight device card connectors 14a-14h per PCI bus 18a or 18b, as illustrated.
Increased processor performance, increased I/O functions and higher I/O bandwidths are required to increase high performance for a computer device. This translates into a requirement for a large number of device card connectors 14a-14h for connecting to the PCI busses 18a, 18b. One approach to increasing the number of available device card connectors 14a-14h is to connect two PCI buses 18a to 20a or 18b to 20b using a PCI-to-PCI bus bridge 22a or 22b, as shown in FIG. 2. A disadvantage of using PCI-to-PCI bus bridges 22a and 22b is that the connections require additional signals and involves two device card connectors 14h and 14i on the motherboard 12. That is, one device card connector 14(h) is required from the parallel PCI busses 18a and 18b, and one device card connector 14(i) is required from the PCI busses 20a and 20b. Consequently, dual busses are less efficient and may utilize a different interface with crossovers between adjacent device card connectors or with large double slot device card assemblies.
Another approach to increase the load and expansion capabilities of the PCI bus is disclosed in the U.S. Pat. No. 5,887,144 to Guthrie et al. Guthrie et al. discloses a primary PCI bus, a plurality of secondary PCI busses for connecting a plurality of additional device cards, and a plurality of switches for connecting the primary PCI bus to a corresponding one of the secondary PCI busses. The device card connectors, i.e., load capabilities of the primary PCI bus, are expanded via the use of the switches connecting a secondary PCI bus to the primary PCI bus.
PCI device card connector expansion is also disclosed in U.S. Pat. No. 5,696,949 to Young. An asynchronous PCI-to-PCI bridge for insertion into a host PCI device card connector is coupled via a cabled PCI bus to an expansion module. An expanded number of device card connectors are thereby available to the host system via the expansion module. Yet another approach to increase PCI device card connectors is disclosed in U.S. Pat. No. 5,764,924 to Hong. Hong discloses an apparatus for extending a PCI bus interface to a remote I/O backplane through a high speed serial link providing a larger number of I/O device card connectors.
While the above described approaches increase the number of device card connectors on a PCI bus, there is still a continuing need to increase the load and expansion capabilities of the PCI bus, particularly without requiring external connections or non-standard sized device cards.
In view of the foregoing background, it is therefore an object of the present invention to increase the load and expansion capabilities of the PCI bus without requiring external connections.
This and other objects, advantages and features in accordance with the present invention are provided by a computer device comprising an interface board, a plurality of busses on the interface board, and a plurality of device card connectors carried by the interface board. The plurality of device card connectors preferably comprises at least one first device card connector coupled to first and second busses synchronous with one another, and at least one second device card connector coupled to the second bus and to a third bus asynchronous with the second bus.
The busses are connected so that the busses may preferably be added in groups according to the number of connectors supported by the interface board, and not by the loading limitations of the PCI busses. Moreover, external connections are not required for connecting the busses together. By defining both synchronous and asynchronous device card connectors, device cards requiring either synchronous or asynchronous communications may be utilized by the computer device. A first bus clock is preferably connected to the first and second busses, and a second bus clock is connected to the third bus.
Each device card may include an interface bridge for connecting to a respective asynchronous or synchronous device card connector. Each device card may also preferably include a processor. The computer device preferably further comprises at least one third device card connector coupled to the third bus and to a fourth bus synchronous with the third bus, and at least one fourth device card connector coupled to the fourth bus and to a fifth bus asynchronous with the fourth bus.
Additional busses are thus added based upon the available number of device card connectors on the interface board. The busses that are synchronous with one another preferably share the same bus clock. Each bus is preferably a peripheral component interface (PCI) bus. The computing device may also be included within a satellite system, where space and weight limitations are critical. The satellite system preferably includes an embedded computer system interfacing with the plurality of busses linked together.
Another aspect of the invention is a method for configuring a plurality of device card connectors on an interface board in a computer device comprising a plurality of busses on the interface board. The method preferably comprises connecting at least one first device card connector to first and second busses synchronous with one another, and connecting at least one second device card connector to the second bus and to a third bus asynchronous with the second bus. The method preferably further comprises connecting at least one third device card connector to the third bus and to a fourth bus synchronous with the third bus, and connecting at least one fourth device card connector to the fourth bus and to a fifth bus asynchronous with the fourth bus.